PIC18F46K80-I/P【PDF 77/351 页】MCU PIC 64KB FLASH 40DIP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3850

73页 74页 75页 76页 [77页]78页 79页 80页 81页

PIC18F66K80 FAMILY

DS39977F-page 168

2010-2012 Microchip Technology Inc.

10.6

INTx Pin Interrupts

External interrupts on the RB0/INT0, RB1/INT1,

RB2/INT2 and RB3/INT3 pins are edge-triggered. If the

corresponding INTEDGx bit in the INTCON2 register is

set (= 1), the interrupt is triggered by a rising edge. If

that bit is clear, the trigger is on the falling edge.

When a valid edge appears on the RBx/INTx pin, the

corresponding flag bit, INTxIF, is set. This interrupt can

be disabled by clearing the corresponding enable bit,

INTxIE. Before re-enabling the interrupt, the flag bit

(INTxIF) must be cleared in software in the Interrupt

Service Routine.

All external interrupts (INT0, INT1, INT2 and INT3) can

wake up the processor from the power-managed

modes, if bit, INTxIE, was set prior to going into the

power-managed modes. If the Global Interrupt Enable

bit (GIE) is set, the processor will branch to the interrupt

vector following wake-up.

The interrupt priority for INT1, INT2 and INT3 is

determined by the value contained in the Interrupt

Priority

bits,

INT1IP

(INTCON3<6>),

INT2IP

(INTCON3<7>) and INT3IP (INTCON2<1>).

There is no priority bit associated with INT0; it is always

a high-priority interrupt source.

10.7

TMR0 Interrupt

In 8-bit mode (the default), an overflow in the TMR0

00h) will set flag bit, TMR0IF. In 16-bit

mode, an overflow in the TMR0H:TMR0L register pair

(FFFFh

0000h) will set TMR0IF.

The interrupt can be enabled/disabled by setting/clearing

enable bit, TMR0IE (INTCON<5>). Interrupt priority for

Timer0 is determined by the value contained in the inter-

rupt priority bit, TMR0IP (INTCON2<2>). For further

details on the Timer0 module, see Section 13.0 “Timer0

Module”

10.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>), and

each individual pin can be enabled/disabled by its

corresponding bit in the IOCB register.

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

REGISTER 10-20: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER

R/W-0

U-0

IOCB7(1)

IOCB6(1)

IOCB5(1)

IOCB4(1)

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

IOCB<7:4>:

Interrupt-on-Change PORTB Control bits(1)

= Interrupt-on-change is enabled

= Interrupt-on-change is disabled

bit 3-0

Unimplemented:

Read as ‘0’

Note 1:

Interrupt-on-change also requires that the RBIE bit of the INTCON register be set.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式